The present invention generally relates to memory devices, and more particularly to a dynamic random access memory having an improved operational stability.
Dynamic random access memories store information in a memory cell capacitor in the form of electric charges. The device has a simple semiconductor structure and can be fabricated easily with a very large integration density. Thus, dynamic random access memories are particularly suitable for realizing high-speed, large capacity storage devices.
In dynamic random access memories, it is well known that a refreshing procedure is necessary for maintaining the information. In the refreshing process, the memory cell capacitor is re-charged in compensation for the loss of electric charges that may be caused by the leakage current or other various reasons such as reading. More specifically, the information stored in the memory cell capacitor is detected by a sense amplifier and the sense amplifier re-writes the information into the memory cell capacitor in the form of electric charges.
Typically, such a refreshing cycle is activated by providing a predetermined time relationship between the /RAS signal used for activating the row address selection and the /CAS signal used for activating the column address selection. More specifically, the timing of the /CAS signal is advanced with respect to the timing of the /RAS signal at the beginning of the refreshing cycle, while the end of the refreshing cycle is marked by the trailing edge of the /CAS signal or /RAS signal. Such a procedure is known as CBR (CAS-before-RAS) process. During the refreshing cycle, the output of the memory device is held at a high impedance state such that no output of information occurs. Thus, conventional dynamic random access memories require a complex control system at the peripheral part thereof for effecting the refreshing cycle.
FIG. 1 shows the construction of a conventional dynamic random access memory in the form of a block diagram.
Referring to FIG. 1, the dynamic random access memory includes a row address buffer circuit 1 supplied with multiple-bit address data A0-An for latching the same and a row decoder 2 that selects a word line from a memory cell array 3 based upon the address data latched in the address buffer circuit 1. As usual, the memory cell array 3 includes a number of memory cells 3a arranged in rows and columns, wherein a number of word lines are provided, extending in the row direction. Further, a number of bit lines are provided, extending in the column direction. Further, the illustrated device includes a column address buffer circuit 4 supplied with multiple-bit address data A0-An for latching the same and a column decoder 5 that selects one of the bit lines from the memory cell array 3 based upon the address data latched in the address buffer circuit 4.
In the dynamic random access memories in general, the address data A0-An are supplied to the address buffers 1 and 2 with an address-multiplexing sequence such that the row address data is supplied first and the column address data is supplied after the row address data. Further, in order to distinguish the timing of the row address data and the column address data, a /RAS (row address strobe) signal and a /CAS (column address strobe) signal are supplied externally. In the illustrated example, the /RAS signal is supplied to a RAS control circuit 15 via an input pad 14, while the /CAS signal is supplied to a CAS control circuit 15 via another input pad 16.
Once a word line and a bit line are selected, the data stored in the memory cell at the intersection of the selected word line and the selected bit line is detected by a sense amplifier that is provided in a sense amplifier array 6, and the data thus detected is transferred to an output buffer circuit 8 via a column gate array 7. When writing data, on the other hand, a write enable signal /WE is supplied to a write clock generator 13 via an input pad 12, and a write clock produced by the write clock generator 13 activates an input buffer circuit 11. Thereby, input data D.sub.in supplied to an input pad 10 is transferred to the sense amplifier array 6 from the buffer amplifier 11 and is written into the selected memory cell via the column gate array 7.
There, the CAS control circuit 17 not only controls the column decoder 5 but also the write clock generator 13 as well as the output buffer circuit 8 such that the output buffer circuit 8 and the write clock generator 13 are enabled in the normal write cycle. More particularly, the CAS control circuit 17 controls the output buffer circuit 8 such that the output impedance of the circuit 8 becomes high during the refreshing cycle.
In such a control operation of the CAS control circuit 17, various thresholding processes are included to discriminate the logic level of the /RAS signal and the /CAS signal. Conventionally, there has been a problem in that, depending on the sharpness of the leading and trailing edges of the /RAS signal and the /CAS signal, the timing of enabling and disabling of the buffer circuit 8 may be changed. In the worst case, such a deviation in the operational timing can lead to a premature enabling of the buffer circuit 8 while the refreshing cycle is still continuing. Hereinafter, this problem will be examined in detail with reference to FIG. 2 showing a part 18 of the circuit of FIG. 1.
Referring to FIG. 2, the circuit 18 includes a first stage circuit 19 for producing a control signal S100 the waveform of which is shown in FIGS. 4(A) and 4(B), in response to the /RAS signal and with a predetermined timing relative to the /RAS signal. The control signal S100 is supplied on the one hand to a circuit 20 that produces a control signal S101 shown in FIGS. 6(A)-6(D) and on the other hand to a circuit 22 that produces a control signal S103 shown in FIGS. 9(A)-9(F), wherein the control signal S103 is supplied from the circuit 20 to an address control circuit 21A together with the control signal S100, and the address control circuit 21A activates the column address buffer circuit 4 and the column decoder 5. The circuit 22, on the other hand, controls the output buffer circuit 8 by the control signal S103 that is supplied to an output control circuit 25.
Further, the circuit 19 supplies the control signal S100 to a circuit 23A that is provided for detecting the commencement of a refreshing cycle, and the circuit 23A supplies an output control signal S121 to a control circuit 24A that produces an output control signal S102 for controlling the output control circuit 25. Thus, the output control circuit 25 is supplied with the control signals S103 and S102 respectively from the circuits 22 and 24A and further with the control signal S100 from the circuit 19, and controls the operation of the output buffer circuit 8 such that the output buffer circuit 8, is at a high impedance state during the refreshing cycle.
FIG. 3 shows the construction of the circuit 19 and FIGS. 4(A) and 4(B) show the timing of producing the output signal S100 in response to the /RAS signal.
Referring to FIG. 3, the circuit 19 includes inverters 26 and 27 connected in series to the input pad 14 such that the /RAS signal supplied to the input pad 14 is delayed by a predetermined time interval that is determined by the number of stages of the inverters. In the illustrated example, two inverters 26 and 27 are used. Thereby, the output control signal S100 is produced in response to the /RAS signal with a predetermined delay therefrom.
FIG. 5 shows the construction of the circuit 20, wherein the circuit 19 is illustrated together by a broken line.
Referring to FIG. 5, the circuit 20 includes a NOR gate 28 and an inverter 29 cascaded with each other, wherein the output signal S100 of the circuit 19 is supplied to a first input terminal of the NOR gate 28 and the /CAS signal at the input pad 16 is supplied to a second input terminal of the NOR gate 28. The output of the NOR gate 28 is inverted in the inverter 29 and forms the output control signal S101 with a timing as indicated in FIG. 6(D). Thus, the signal S101 is at a low level state when both the signal S100 and /CAS have the low level state.
FIG. 7 shows the construction of the address control circuit 21A, wherein it will be noted that the address control circuit 21A includes a circuit 21a that in turn is formed of inverters 211 and 212 cascaded with each other, and the output of the circuit 21a is supplied to the address buffer circuit 4 that includes transistors 4a-4d connected in series between two power supply voltage sources wherein the transistors 4a and 4b are formed of a P-channel MOS transistor while the transistors 4c and 4d are formed of an N-channel MOS transistor. The output of the circuit 21a is supplied directly to the gate of the transistor 4d and further to the gate of the transistor 4a after inversion by an inverter 4e. Further, an address signal An is supplied to the gate of the transistors 4b and 4c after inversion in an inverted 4f. The output of the transistor circuit is obtained at an intermediate node between the transistors 4b and 4c and is latched by a latch circuit formed of inverters 4g and 4h. The output of the address buffer circuit 4 is then supplied to the column decoder 5 that is formed of a multiple input NAND gate 5a and an inverter 5b cascaded thereto, wherein the address data of other address bits such as A.sub.n-1, . . . A.sub.0 are supplied to the gate 5a. The output of the inverter 5b is outputted on the column line CL as usual.
FIG. 8 shows the construction of the circuit 22 for producing the control signal S103 for controlling the activation of the output buffer circuit 8, wherein the circuit 22 includes a NAND gate 30, a NOR gate 21 and inverters 32 and 33 connected to form a flip-flop circuit, wherein the NAND gate 30 and the inverter 32 are connected in series to produce an signal S02, and the signal S02 thus produced is supplied to the NOR gate 31 that is connected in series to the inverter 33. The inverter 33 in turn produces a signal S01 that is fed back to the NAND gate 30. Further, the control signal S100 is supplied to the NAND gate 30 from the circuit 19 in response to the /RAS, while the /CAS signal is supplied from the input pad 16 to the NOR gate 31. Thus, the output signal S103 is produced by the signal S01 that has passed consecutively through inverters 34 and 35 that in turn are provided for the timing adjustment.
FIGS. 9(A)-9(F) show the operation of the circuit 22, a timing control circuit for producing the output control signal S103 in response to the /RAS and /CAS signals represented in FIGS. 9(A) and 9(B) as well as the signal S100 represented in FIG. 9(C), wherein it will be noted that the signal S01 undergoes a transition to the low level state in response to the leading edge of the /CAS signal and an opposite transition to the high level state in response to the trailing edge of the same /CAS signal, provided that the level of the signal S02 is held at the low level state in correspondence to the normal read cycle of the dynamic random access memory. On the other hand, when the level of the signal S02 is high in correspondence to the initial period of the refreshing cycle, the signal S01 does not undergo a transition immediately to the low level state even when the /CAS signal has undergone a transition to the low level state. Only when the signal S02 has undergone a transition to the low level state in correspondence to the transition of the /RAS signal that in turn occurs in correspondence to the refreshing cycle, the signal S01 undergoes a transition to the low level state. The signal S01 further undergoes another transition to the high level state in correspondence to the transition of the /CAS signal to the high level state.
On the other hand, the signal S02 experiences a transition to the low level state in the normal read cycle in response to the transition of the /RAS signal, and hence the signal S100 also experiences a transition to the low level state, irrespective of the state of the signal S01, wherein the low level state of the signal S02 continues until the signal S01 undergoes a transition to the high level state. Further, in the refreshing cycle, the signal S02 undergoes a transition to the low level state in response to the leading edge of the /RAS signal and maintains the low level state until the /RAS signal returns to the high level state.
In correspondence to the signal S01, the output control signal S103 is produced as indicated in FIG. 9(F), as a signal identically shaped as signal S01 but delayed therefrom by the timing of the inverters 34 and 35. The control signal S103 thereafter supplied to the circuit 25 for controlling the output buffer circuit 25, as already noted, wherein the output buffer circuit 8 is activated in response to the low level interval of the signal S103, while the same output buffer circuit 8 is deactivated in response to the high level state of the signal S103. During the high level state of the control signal S103, the output buffer circuit 8 exhibits a high output impedance state.
Next, the circuit 23A of FIG. 2 for detecting the CBR refreshing cycle will be described with reference to FIG. 10.
Referring to FIG. 10, the circuit 23A includes an inverter 23a, a NAND gate 23b connected in series to the inverter 23a for receiving an output signal U01 therefrom along a first path, an inverter 23c interposed in another path extending from the inverter 23a to the NAND gate 23b, an inverter 23d connected to the NAND gate 23b for inverting an output signal U02 of the gate 23b to produce an output signal U03, a NAND gate 23e supplied with the signal U03 and the signal S101 via an inverter 23f wherein the inverter 23f produces an output signal U07 as a logic inversion of the signal S101. Thereby, the NAND gate 23e produces an output signal U05, and the signal U05 is supplied to a NAND gate 23g that forms a flip-flop circuit together with another NAND gate 23h to which the output signal U07 of the inverter 23f is supplied. In the flip-flop circuit, the NAND gate 23g produces an output signal U06 that is supplied to the NAND gate 23h, and the NAND gate 23h produces an output control signal S121 that indicates the commencement of the CBR refreshing cycle.
Next, the operation of the circuit 23A will be described in detail with reference to FIGS. 11(A)-11(K), wherein FIGS. 11(A)-11(C) represent the signals /RAS, /CAS and S100, respectively.
It will be noted that the signal U01 experiences a transition to the high level state in correspondence to the leading edge of the signal s100 and returns to the low level state in response to the trailing edge of the signal S100, wherein the leading edge and trailing edge of the signal S100 correspond to the leading edge and trailing edge of the /RAS signal. Further, the signal U02 causes a momentary transition to the low level state in correspondence to the leading edge of the signal U01. Further, the signal U03 is produced as a logic inversion of the signal U02, and the signal U07 is produced as a logic inversion of the signal S101.
Further, the signal U05 experiences a transition to the low level state in response to the leading edge of the signal S100 and a transition to the high level state in response to the trailing edge of the /CAS signal or the trailing edge of the /RAS signal, whichever comes first. Thus, when the trailing edge of the /CAS signal, comes before the trailing edge of the /RAS signal as indicated in the drawing by "A," the signal U05 is reset in response to the trailing edge of the /CAS signal. In addition when the trailing edge of the /RAS signal appears before the trailing edge of the /CAS signal, as indicated by "B," the signal U05 is reset in response to the trailing edge of the /RAS signal. Further, the signal U06 experiences a transition to the high level state in response to the leading edge of the signal U05 and a transition to the low level state in response to the trailing edge of the signal U05. Thereafter, the output signal S121 is obtained in correspondence to the signal U06.
It should be noted in FIGS. 11(A)-11(K) that the signal S121 is not produced in the normal read write cycle. This is because the signal S101 takes a high level state in the normal read cycle when the signal U03 has caused the transition in response to the signal S100. In other words, the signal S121 is produced only when the /CAS signal has preceded the /RAS signal. Further, the signal S121 is reset by the trailing edge of the /CAS signal, or /RAS signal whichever appears first.
Next, the construction of the CBR control circuit 24A will be described with reference to FIG. 12.
Referring to FIG. 12, the circuit 24A includes a number of inverters 24a-24f cascaded in series, and the inverter 24f supplies an output signal to a NAND gate 24g. Further, an output V01 of the inverter 24c included in the cascaded inverters is supplied directly to the NAND gate 24g as another input signal, and the NAND gate 24g produces an output signal V02 as a result of the logic combination of the output of the inverter 24f and the output of the inverter 24c. The output of the NAND gate 24g in turn is supplied to a NAND gate 24h that forms a flip-flop circuit together with a NAND gate 24i, wherein the NAND gate 24i is supplied with an output signal V03 that is produced by an inverter 24g in response to the control signal S101. In the flip-flop circuit, the NAND gate 24h produces the output signal S102 and the signal S102 thus produced is fed back to the NAND gate 24i. The NAND gate 24i in turn produces an output signal V04 and supplies the same to the NAND gate 24h.
FIGS. 13(A)-13(J) show the operation of the CBR control circuit 24A, wherein FIGS. 13(A) and 13(B) show the waveform of /RAS signal and /CAS signal, while FIG. 13(C) shows the waveform of the signal S100 and FIG. 13(D) shows the waveform of the signal S121. Further, FIG. 13(E) shows the waveform of the signal S101. In addition, FIGS. 13(F)-13(I) show the waveform of the signals V01-V04, respectively, and FIG. 13(J) shows the waveform of the signal S102.
Referring to the drawings, the signals S100, S121 and S101 are produced with the timing sequence already described, and the signal V01 is produced as a logic inversion of the signal S121 with a predetermined delay therefrom. Further, the signal V02 is produced in correspondence to the leading edge of the signal V01 and continues for an interval determined by the delay caused by the inverters 24d-24g. The signal V03 is produced as a logic inversion of the signal S101. Moreover, the signal V04 is produced in response to the signals V03 and S102 and undergoes a transition to the low level state in response to the leading edge of the signal S102. Further, the signal S102 is produced in response to the leading edge of the signals V02 and V04. There, the signal V04 maintains the low level state until the signals V03 and S102 undergoes a transition to the low level state. Similarly, the signal S102 maintains the high level state until the signal V04 causes a transition to the low level state.
As indicated in FIGS. 13(A)-13(J), the trailing edge of the signals S102 is determined by the timing of the trailing edge of the /CAS signal or the /RAS signal whichever comes first. Thus, as indicated in "A" in FIGS. 13(A)-13(J), the control signal S102 is reset in response to the timing of the trailing edge of the /CAS signal when the /CAS signal ends before the /RAS signal. Similarly, the reset of the control signal S102 occurs in response to the trailing edge of the /RAS signal, as indicated by "B" in the figures in the case when the trailing edge of the /RAS signal causes before the trailing edge of the /CAS signal.
Next, the circuit 25 for controlling the output buffer circuit 8 in response to the control signals S100, S102 and S103 will be described with reference to FIG. 14.
Referring to FIG. 14, the circuit 25 includes an inverter 25a supplied with the output control signal S100 for inverting the same to produce an output signal W01, wherein the signal W01 is supplied to a NAND gate 25b. Further, inverter 25c is supplied with the control signal S102 and produces a signal W02 as a logic inversion thereof. The signals W01 and W02 are supplied to a NAND gate 25b, wherein the NAND gate 25b produces an output signal W03 and supplies the same to an inverter 25d that produces an output signal W04 as a logic inversion of the signal W03. The signal W04 is then supplied to another NAND gate 25e that is further supplied with a signal W05 from an inverter 25f as a logic inversion of the signal S103. Thereby, the NAND gate 25e produces an output that is passed through an inverter 25g to form a control signal S111. The signal S103 is further supplied to a NOR gate 25h that is also supplied with the same signal S103 but with a delay caused by inverters 25i and 25j, wherein the gate 25h produces a control signal S112.
The control signals S111 and S112 are used for controlling the output buffer circuit 8 of which construction is shown in FIG. 15.
Referring to FIG. 15, the circuit 15 includes a NAND gate 8a supplied with the control signals S111 and S112 to produce a signal X01 which is inverted subsequently by an inverter 8b to produce a signal X02. The signal X02 in turn is supplied to a transfer gate 8c formed of an N-channel MOS transistor and causes a transfer of data S141 outputted from a sense amplifier in the sense amplifier array 6 to a NAND gate 8d as a signal X11 in response to the high level state of the signal X02. The NAND gate 8d is supplied with the signal S112 in addition to the signal X11 and produces a signal X12 that is latched by a flip-flop circuit formed by the gate 8d and a feedback path 8e. The output signal X12 of the gate 8d is supplied to a gate of an N-channel MOS transistor 8g for controlling the conduction thereof.
Further, the data S141 is supplied to another transfer gate 8i after passing through an inverter 8h, wherein the transfer gate 8i is formed of an N-channel MOS transistor similarly to the transistor 8c and is activated in response to the control signal X02 from the inverter 8b. Thus, the data that has passed through the transfer gate 8i is represented as a signal X21, wherein the signal X21 is supplied to a NAND gate 8j which is also supplied with the control signal S112. Again, the NAND gate 8j has a feedback path provided by an inverter 8k and forms a flip-flop circuit for latching the signal X21. The NAND gate 8j thereby produces an output signal X22 that is inverted subsequently in an inverter 81 with respect to the logic state thereof to form a signal X23 that is supplied to a gate of another N-channel MOS transistor 8m. There, the transistors 8g and 8m are connected in series between the voltage sources Vcc and Vss, and the output of the buffer circuit 8 is obtained at the output pad 9 that is connected to an intermediate node between the transistors 8g and 8m.
It should be noted that the low level state of the signal S111 causes a turning off of transfer gate transistors 8c and 8i, and the flip-flop circuit formed of the circuits 8c and 8e as well as the flip-flop circuit formed of the circuits 8j and 8k continue outputting the signals X12 and X22, provided that the signal S112 takes the high level state. When the signal S111 is in the high level state, on the other hand, the data signal S141 is supplied to the flip-flop circuits and is latched therein.
When the signal S112 has caused a transition to the low level state, on the other hand, the data latching by the flip-flop circuit is deactivated and the output signals X12 and X22 are both urged to the high level state. Thereby, the transistors 8g and 8m are both turned off and the output of the buffer circuit 8 takes the high impedance state. In summary, the output buffer circuit 8 outputs data when the signal S112 is in the high level state. When the signal S112 is in the low level state, the buffer circuit 8 shows the high impedance state.
Next, the operation of the circuit 25 will be described with reference to FIGS. 16(A)-16(L), wherein FIGS. 16(A) and 16(B) show the /RAS signal and the /CAS signal respectively, FIGS. 16(C)-16(E) show the control signals S100, S102 and S103 respectively, FIGS. 16(F)-16(J) show the signals W01, W02, W03, W04 and W05 respectively, and FIGS. 16(K) and 16(L) show the signals S111 and S112, respectively.
Referring to FIGS. 16(A)-16(L), the signal W01 corresponds to the signal S100 and undergoes a transition to the high level state and a transition to the low level state in response to the leading edge and the trailing edge of the signal S100. Similarly, the signal W02 corresponds to the signal S102 and undergoes a transition in response thereto. The signal W03 thereby causes a transition in response to the signal W01 and exhibits a low level state in the normal read cycle in correspondence to the high level state of the signal W01. Further, the signal W03 causes a momentary transition to the low level state in the CBR refreshing cycle in response to the interval after the signal W01 has undergone a transition to the high level state but before the signal W02 changes to the low level state. In response the signal W03, the signal W04 is produced as a logic inversion. Referring to FIGS. 16(H) and 16(I), it will be noted that the momentary transition of the signal W03 and hence the signal W04 occurs twice, the first during the interval in which the /CAS signal is low and the second during the interval after the /CAS signal has returned to the high level state.
The signal W05 represents a logic inversion of the signal S103 and controls the gate 25e such that the signal W04 is selectively passed therethrough in response to the high level interval of the signal W05. Thereby, the signal W04 that has passed through the gate 25e is passed further through the inverter 25g to form the signal S111. There, it will be noted that the signal S111 includes a high level state in correspondence to the /CAS signal in the normal read cycle and a momentary high level state in the CBR refreshing cycle in correspondence to the high level state of the signals W03 and W04. It should be noted that the signal S111 causes a latch operation of the output buffer circuit 8 in response to the low level state, while the latch is released in response to the high level state of the signal S111.
The signal S112 in turn is produced in response to the transition of the signal S103 that in turn is caused by the transition of the /CAS signal in the normal read cycle. In the CBR refreshing cycle, on the other hand, the signal S103 undergoes a transition to the low level state in response to the leading edge of the /RAS signal and a subsequent transition to the high level state in response to the trailing edge of the /CAS signal. Thereby, the signal S112 is also activated to the high level state in response to the leading edge of the /RAS signal and deactivated to the low level state in response to the trailing edge of the /CAS signal.
Referring to FIGS. 16(K) and 16(L) again, it will be noted that there exists a moment wherein the signals S111 and S112 are both high in the normal read cycle and the data output occurs in response to such a timing sequence wherein the signals S111 and S112 are both high. On the other hand, such a state does not exist in the refreshing cycle. There, the signal S111 causes a transition to the high level state momentarily in correspondence to the signals W03 and W04 before the signal S112 undergoes a transition to the high level state. However, such a transition of the signal S111 during in the low level interval of the signal S112 does not cause the data output and the output buffer circuit 8 remains in the high impedance state. When the signal S112 has caused a transition to the high level state subsequently to the momentary transition of the signal S111, on the other hand, the signal S111 is low in the high level interval of the signal S112, and the signals X12 and X22 are latched at the low level state. Thereby, the transistors 8g and 8m are both turned off and the output of the buffer circuit 8 is held also at the high impedance sate. Therefore, data output is prohibited during the refreshing cycle of the device.
On the other hand, there is a possibility that the signal S102 experiences a premature transition to the low level state when the /CAS signal rises gradually. Hereinafter, the problem of the conventional circuit described heretofore will be examined with reference to FIGS. 17(A)-17(L) showing the waveform of the signals shown in FIGS. 16(A)-16(L) for the case where the /CAS signal rises slowly as indicated in FIG. 17(B). Such a slow rise of the /CAS signal may be caused for example by the parasitic capacitance of the wiring used for transferring the /CAS.
It is important to note that the signal S111 undergoes a transition to the high level state in response to the leading edge of the signal W04, provided that the signal W05 maintains the high level state. See the circuit diagram of FIG. 14. There, such a transition of the signal W04 to the high level state can be induced not only in response to the leading edge of the /RAS signal but also in response to the trailing edge of the /CAS signal, as already noted in FIG. 16(I). In the normal operation of the device as represented in FIGS. 16(A)-16(L), it will be noted that the high level state of the signal W04 occurring in response to the trailing edge of the /CAS signal does not cause the output of the signal S111 because of the low level state of the signal W05. In the example of FIGS. 17(A)-17(L) on the other hand, the output of the signal S111 occurs because of the premature transition of the signal S102 in response to the gradual increase of the /CAS signal level, as shown in FIGS. 17(B) and 17(D). Therefore, an unwanted data output occurs during the CBR refreshing cycle and the operational specification of the dynamic random memory device for maintaining the output the output buffer amplifier at the high impedance state during the refreshing cycle is no longer satisfied.
The foregoing analysis of operation of various parts of the memory device of FIG. 2 indicates that the cause of the undesirably result is attributed to the independently conducted thresholding operation for detecting the trailing edge of the /CAS signal in the circuit 24A and in the circuit 22. Thus, the circuit 24A produces the signal S102 based upon the signal S101 that in turn is produced in the circuit 20, while the signal S103 is produces in the circuit 22. Therefore, when the signals S102 and S103 are produced based upon the same thresholding operation of the /CAS signal, the deviation of timing between the signal S102 and the signal S103 would be eliminated and the problem of undesirable data output during the CBR refreshing cycle will also be eliminated.